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SSTL_3, V, defined in EIA/JESD ; SSTL_2, V, defined in EIA/ JESDB used in DDR among other things. SSTL_18, V, defined in. STUB SERIES TERMINATED. LOGIC FOR VOLTS (SSTL_2). EIA/JESD SEPTEMBER ELECTRONIC INDUSTRIES ALLIANCE. JEDEC Solid State . SSTL (JESD, JESDB, JESD). • HSTL (JESD). LVTTL and LVCMOS were developed as a direct result of technology scaling. With each reduction in.

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Almost representatives, appointed by some JEDEC member companies work together in 50 JEDEC committees to meet the needs of every segment of the industry, manufacturers and consumers alike.

The dc values are chosen such that the final logic state is unambiguously defined, that is once the receiver input has crossed this value, the receiver will change to and maintain the new 9h state.

Compliant devices must meet the VSwing ac specification under actual use conditions. If the driver outputs are sized for this condition, then for all other VDDQ voltage applications, the resulting input signal will be jesv8 than the minimum mV.

This clause is added to set the conditions under which the driver ac specifications can be tested. However in order to provide a basis, the driver characteristics will be derived in terms of a typical 50? The first clause defines pertinent supply voltage requirements common to all compliant ICs.

Under these conditions VOH is 1. By downloading this file the individual agrees not to charge for or resell the resulting material. In this non binding section we will show some derived applications. In this example a Class II type buffer might be preferred since it comes closer, in conjunction with the series resistor, to match the characteristic impedance of the transmission line.


While driver characteristics are derived from a 50? The relationship of the different levels is shown in figure 1.

Stub Series Terminated Logic

Kesd8 3 shows the typical dc environment that the output buffer is presented with. The test circuit is assumed to be similar to the circuit shown in figure 5. Vx ac indicates the voltage at which differential input signals must be crossing.

The ac values are chosen to indicate the levels at which the receiver must meet its timing specifications.

JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles, materials, or processes. JEDEC is the leading developer of standards for the solid-state industry, they have published over documents to date.

Viso Parameter Input clock signal offset voltage Viso variation Min. AC test conditions may be measured under nominal voltage 9v as long as the supplier can demonstrate by analysis, that the device will meet its timing specifications under all supported voltage conditions.

No claims to be in conformance with this standard may be made unless all requirements stated in the standard are jrsd8. The third clause specifies the minimum required output characteristics of, and ac test conditions for, compliant outputs targeted for various application environments. In order to meet the mV minimum requirement for VIN, a minimum of 8. If you have downloaded the file prior to date of errata please reprint page 7.

The system designer can be sure that the device will switch state a certain amount of time after the ejsd8 has crossed ac threshold and not switch back as long as the input stays beyond the dc threshold.

F or info rm ationcon tact: The standard is particularly intended to improve operation in situations where busses must be nesd8 from relatively large stubs.

EIA JEDEC STANDARD jesdb-sstl_2_百度文库

The test circuit is assumed to be similar to the circuit shown in figure 4. Making this distinction is important for the design jedd8 high gain, differential, receivers that are required. One advantage of jfsd8 approach is that there is no need for a VTT power supply.


JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally.

See also figure 2.

Units V V Notes 2. The second clause defines the minimum dc and ac input parametric requirements and ac test conditions for inputs on compliant devices. An example of this is shown in figure 6. This can be expressed by equation-1 or equation An example of this may be address drivers on a memory board.

In that case, the designer may decide to eliminate the series resistors entirely.

The standard defines a reference voltage VREF which is used at the receivers as well as a voltage VTT to which termination resistors are connected. An example of ringing is illustrated in the dotted wave-form. The information included in JEDEC standards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. In some standards this ratio equals 0.

Busses may be terminated by resistors to an external termination voltage.

Stub Series Terminated Logic

An example is shown in figure 7. With a series resistor of 25? VTT is specified as being equal to 0. An example is shown in figure 8.